Chenchang Zhan received the B.Sc. degree in electrical engineering and the M.Sc. degree in microelectronics from Fudan University, Shanghai, China, in 2004 and 2007, respectively, and the Ph.D. degree in electronic and computer engineering from the Hong Kong University of Science and Technology (HKUST), Hong Kong SAR, China, in 2011. From 2006 to 2007, he was an Intern Analog Design Engineer with VeriSilicon, Shanghai, China. From 2011 to 2012, he worked as a post-doctoral Research Associate with HKUST. From 2012 to 2014, he was with Qualcomm Inc., San Diego, CA, as a Senior Engineer, focusing on the design of high-performance power converters for future generations of mobile devices. In 2014, he joined the Southern University of Science and Technology (SUSTech), Shenzhen, China, where he is currently an Assistant Professor with School of Microelectronics (National Exemplary School of Microelectronics). His research interests include the analysis and design of analog, mixed-signal and power management integrated circuits and systems for a variety of applications. Up to date, he published 1 book, >60 SCI/EI papers, and was granted with 6 China and 5 US patents. He received the Best Paper Award from IEEE ISIC'2009, Singapore and IEEE EDSSC'2018, Shenzhen, the Best Student Paper Award from IEEE EDSSC'2010, Hong Kong, the Best Student Paper Award from IEEE ISCAS'2011, Rio de Janeiro, Brazil, the 2018 SUSTech Young Faculty Research Award, the 2019 SUSTech Excellent Teacher of the Year Award, and the 2019 SUSTech Excellent Residential College Mentor of the Year Award. He served as a Review Committee Member for IEEE APCCAS'2014, a Technical Program Committee member for IEEE ICTA'2018 and ICTA’2019, a Guest Editor for Hindawi APEC, a Session Chair/Co-Chair for IEEE ISCAS'2018, ISCAS'2019 and ICTA'2018, as well as a reviewer for many reputational international journals and conferences. He is a Senior Member of IEEE.
2007-2011, Ph.D. in electronic and computer engineering, Hong Kong University of Science and Technology
2004-2007, M.Sc. in microelectronics, Fudan University
2000-2004, B.Sc. in electrical engineering, Fudan University
2014-present, Assistant Professor, Associate Professor, Southern University of Science and Technology
2012-2014, Senior Engineer, Qualcomm Inc., San Diego, CA
2011-2012, Postdoctoral Research Associate, Hong Kong University of Science and Technology
Power management and energy harvesting integrated circuits and systems
Analog and mixed-signal integrated circuits
Low-power integrated circuit design methodology
ResearcherID Link: https://publons.com/researcher/1807217/chenchang-zhan/
Google Scholar Link: https://scholar.google.com/citations?user=tYZ863gAAAAJ&hl=en
Honors and Awards:
2019, Elevated to be IEEE Senior Member
2019, SUSTech Excellent Teacher of the Year Award
2019, SUSTech Excellent Residential College Mentor of the Year Award
2018, SUSTech Young Faculty Research Award
2018, Best Paper Award, IEEE EDSSC
2017, Excellent Advisor Award, SUSTech Innovation and Entrepreneurship Competition
2016, Excellent Advisor Award, National University IC Design Competition (NUICDC)
2016, SUSTech Excellent Individual for UG Admission Initiatives
2016, SUSTech Shuren Residential College Mentor of the Year Award
2016, Nanshan Leading Talent Tier C, Nanshan District, Shenzhen, Guangdong
2014, Peacock Talent Tier C, Shenzhen, Guangdong
2011, Best Student Paper Award, IEEE ISCAS
2010, Best Student Paper Award, IEEE EDSSC
2009, Best Paper Award, IEEE ISIC
2009, Best Paper Award Nomination, IEEE ISCAS
|J. Lin, L. Wang, C. Zhan and Y. Lu, "A 1-nW Ultra-Low Voltage High PSRR Subthreshold CMOS Voltage Reference with 0.0154%/V Line Sensitivity," IEEE Trans. Circ. Syst. II: Exp. Briefs, vol. 66, no.10, pp. 1653-1657, Oct. 2019. https://doi.org/10.1109/TCSII.2019.2920693.
|G. Cai, C. Zhan and Y. Lu, “A fast-transient-response fully-integrated digital LDO with adaptive current step size control,” IEEE Tran. Circ. Syst. I: Reg. Papers, vol. 66, no. 9, pp. 3610-3619, Sept. 2019. https://doi.org/10.1109/TCSI.2019.2917558.
|L. Wang and C. Zhan, “A 0.7-V 28-nW CMOS subthreshold voltage and current reference in one simple circuit,” IEEE Tran. Circ. Syst. I: Reg. Papers, vol. 66, no. 9, pp. 3457-3466, Sept. 2019. https://doi.org/10.1109/TCSI.2019.2927240.
|Y. Tan, C. Zhan and G. Wang, "A fully-on-chip analog low-dropout regulator with negative charge pump for low-voltage applications," IEEE Trans. Circ. Syst. II: Exp. Briefs, vol. 66, no. 8, pp. 1361-1365, Aug. 2019. https://doi.org/10.1109/TCSII.2018.2881072.
|C. Zhan, G. Cai and W. H. Ki, “A transient-enhanced output-capacitor-free low-dropout regulator with dynamic miller compensation,” IEEE Trans. On Very Large Scale Integration (VLSI) Systems, vol. 27, no. 1, pp. 243-247, Jan. 2019. https://doi.org/10.1109/TVLSI.2018.2867850.
|H. Li, C. Zhan and N. Zhang, "A fully-on-chip digitally assisted LDO regulator with improved regulation and transient responses," IEEE Tran. Circ. Syst. I: Reg. Papers, vol. 65, no. 11, pp. 4027-4034, Nov. 2018. https://doi.org/10.1109/TCSI.2018.2851514.
|Q. Huang, C. Zhan, and J. Burm, “A 30 MHz Voltage-Mode Buck Converter Using Delay-Line-Based PWM Control,” IEEE Trans. Circ. Syst. II: Exp. Briefs, vol. 65, no. 11, pp. 1659-1663, Nov. 2018. https://doi.org/10.1109/TCSII.2017.2764048.
|L. Wang, C. Zhan, J. Tang, Y. Liu and G. Li, “A 0.9V 33.7ppm/ºC 85nW sub-bandgap voltage reference consisting of subthreshold MOSFETs and single BJT,” IEEE Trans. On Very Large Scale Integration (VLSI) Systems, vol. 26, no. 10, pp. 2190-2194, Oct. 2018. https://doi.org/10.1109/TVLSI.2018.2836331.
|C. Huang, C. Zhan, L. He, L. Wang and Y. Nan, "A 0.6V-minimum-supply, 23.5ppm/ºC subthreshold CMOS voltage reference with 0.45% variation coefficient," IEEE Trans. Circ. Syst. II: Exp. Briefs, vol. 65, no. 10, pp. 1290-1294, Oct. 2018. https://doi.org/10.1109/TCSII.2018.2846808.
|Y. Liu, C. Zhan, L. Wang, J. Tang and G. Wang, “A 0.4-V wide temperature range all-MOSFET subthreshold voltage reference with 0.027%/V line sensitivity,” IEEE Trans. Circ. Syst. II: Exp. Briefs, vol. 65, no. 8, pp. 969-973, Aug. 2018. https://doi.org/10.1109/TCSII.2018.2794512.
|L. Wang, C. Zhan, J. Tang and G. Li, “An amplifier-offset-insensitive and high PSRR subthreshold CMOS voltage reference.” Int’l J. Circ. Theor. Appl., vol. 46, no. 2, pp. 259-271, Feb. 2018. href="https://doi.org/10.1002/cta.2383" https://doi.org/10.1002/cta.2383.
|S. Zhao, C. Zhan and G. Cai, “A 2×VDD-enabled output-capacitor-free low-dropout regulator with fast transient response for low-cost system-on-chip,” J. Circ. Syst. Comp., vol. 27, no.9, pp. 1850143-1-17, Jan. 2018. https://doi.org/10.1142/S0218126618501438.
|Y. Liu, C. Zhan and L. Wang, “An ultralow power subthreshold CMOS voltage reference without requiring resistors or BJTs,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 26, no. 1, pp. 201-205, Jan. 2018. https://doi.org/10.1109/TVLSI.2017.2754442.
|Q. Huang, C. Zhan and J. Burm, “A low-complexity locking-accelerated digital PLL with multi-output bang-bang phase detector,” Microelectronics Journal, vol. 67, pp. 19-24, Sept. 2017. https://doi.org/10.1016/j.mejo.2017.07.004.
|L. Wang, C. Zhan, J. Tang, S. Zhao, G. Cai, Y. Liu, Q. Huang and G. Li, “Analysis and design of a current-mode bandgap reference with high power supply ripple rejection,” Microelectronics Journal, vol. 68, pp. 7-13, Aug. 2017. https://doi.org/10.1016/j.mejo.2017.08.011.
|Q. Huang, H. Joo, J. Kim, C. Zhan and J. Burm, “An energy-efficient frequency domain CMOS temperature sensor with switched Vernier time-to-digital conversion,” IEEE Sensors Journal, vol. 17, no. 10, pp. 3001-3011, May 2017. https://doi.org/10.1109/JSEN.2017.2686442.
|C. Zhan and W. H. Ki, “Analysis and design of output-capacitor-free low-dropout regulators with low quiescent current and high power supply rejection,” IEEE Tran. Circ. Syst. I: Reg. Papers, vol. 61, no. 2, pp. 625-636, Feb. 2014 (Top 5 most frequently downloaded paper in Feb. 2014). https://doi.org/10.1109/TCSI.2014.2300847.
|C. Zhan and W. H. Ki, “An output-capacitor-free adaptively biased low-dropout regulator with subthreshold undershoot-reduction for SoC,” IEEE Tran. Circ. Syst. I: Reg. Papers, vol. 59, no. 5, pp. 1119-1131, May 2012 (Invited to Special Issue on ISCAS 2011). https://doi.org/10.1109/TCSI.2012.2190675.
|W. H. Ki, K. M. Lai and C. Zhan, “Charge balance analysis and state transition analysis of hysteretic voltage mode switching converters,” IEEE Tran. Circ. Syst. I: Reg. Papers, vol. 58, no.5, pp. 1142-1153, May 2011. https://doi.org/10.1109/TCSI.2010.2089557.
|C. Zhan and W. H. Ki, “A Low dropout regulator with low quiescent current and high power supply rejection over wide range of frequency for SoC,” J. Circ. Syst. Comp., vol. 20, no. 1, pp. 1-13, Jan. 2011 (Invited to Special Issue on Green Integrated Circuits). https://doi.org/10.1142/S0218126611007037.
|C. Zhan and W. H. Ki, “Output-capacitor-free adaptively biased low-dropout regulator for system-on-chips,” IEEE Tran. Circ. Syst. I: Reg. Papers, vol. 57, no. 5, pp. 1017-1028, May 2010 (Invited to Special Issue on ISCAS 2009). https://doi.org/10.1109/TCSI.2010.2046204.
|C. Zhan, X. Zhou, and D. Zhou, “A low-power high-resolution sigma-delta modulator,” Research & Progress of Solid-State Electronics, vol. 27, no. 3, pp. 375-379, Aug. 2007. https://doi.org/10.3969/j.issn.1000-3819.2007.03.021
|C. Zhan, Y. Wang, X. Zhou, H. Min and D. Zhou, “A deep-submicron sigma-delta ADC design flow,” Research & Progress of Solid-State Electronics, vol. 27, no. 1, pp. 63-68, Feb. 2007. https://doi.org/10.3969/j.issn.1000-3819.2007.01.014|