Faculty
Biography
Dr. Junmin Jiang (S'09-M'18) received his B.Eng. degree in Electronic and Information Engineering from Zhejiang University in 2011 and his Ph.D. degree in Electronic and Computer Engineering from the Hong Kong University of Science and Technology (HKUST) in 2017 under the supervision of Prof. Wing-Hung Ki. From 2018 to 2021, he was an Analog Design Engineer with Kilby Labs Silicon Valley at Texas Instruments (TI), Santa Clara, CA, USA, focusing on cutting-edge power management IC and system design, with extensive industrial R&D and tape-out experience. He holds 39 invention patents, including 27 granted (with 11 international patents granted across the US, Europe, and Japan). He joined Southern University of Science and Technology (SUSTech) as an Assistant Professor in March 2021; was appointed Associate Professor in November 2022; and was promoted to Tenured Associate Professor in November 2026.
His primary research interests include high-current AI computing power chips (intermediate bus converters [IBC], DrMOS power stages, and integrated voltage regulators [IVR]), switched-capacitor converters, ultra-fast transient hybrid converters, Sigma converters, negative-voltage power supplies and Micro-LED drivers, 100V high-voltage converters and liquid cooling drivers, low-power analog circuits and voltage references, as well as deep reinforcement learning for analog circuit sizing and layout generation (AI for EDA). He has authored or co-authored over 90 peer-reviewed papers in prestigious integrated circuit and power electronics venues, including 8 papers in the premier IC conference IEEE ISSCC, 11 papers in leading journals IEEE JSSC / SSCL, and 26 papers in IEEE CAS and Power Electronics flagship journals IEEE TPEL and IEEE TCAS-I/II/JETCAS.
He serves as Chair of the IEEE Circuits and Systems Society (CASS) Shenzhen Chapter and as a member of the IEEE Power and Energy Circuits and Systems (PECAS) Technical Committee; Technical Program Committee (TPC) Member for IEEE CICC, IEEE ISCAS, IEEE ICTA, and IEEE ICSICT; former Associate Editor and Guest Editor (Special Issues on ISCAS 2022 and ISICAS 2022) for the IEEE CAS Society flagship journal IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II); and a frequent reviewer for JSSC, TPEL, TCAS-I/II, TVLSI, SSCL, and other leading international journals.
His honors and awards include: the Analog Devices Inc. (ADI) Outstanding Student Designer Award (2015) and ISSCC Student Travel Grant Award (2015); the IEEE Solid-State Circuits Society (SSCS) Pre-Doctoral Achievement Award (2017) and Solomon Systech Scholarship (2017); the ASP-DAC University LSI Design Contest Special Feature Award (2018); the Texas Instruments Patent Awards (2020); the Shenzhen Overseas High-Level Talent (Peacock Plan, 2021); the National-Level Overseas High-Level Young Talent (2022); the Shenzhen Industrial Development and Innovation Talent Award (2023); the SUSTech Outstanding Teaching Award (2024); the SUSTech Outstanding Residential College Mentor Award (2025) and Top 10 Semiconductor Research Advances in China (Nomination Award, 2025); and the IEEE CICC Best Paper Award (2026), ASP-DAC University LSI Design Contest Best Design Contest Award (2026), and ICSICT Design Contest 1st Award (2026).
Education
2013.09 – 2017.08The Hong Kong University of Science and Technology (HKUST), Electronic and Computer Engineering, Ph.D.
2015.08 – 2016.01University of Macau, State Key Laboratory of Analog and Mixed-Signal VLSI, Visiting Scholar
2007.09 – 2011.06Zhejiang University, Electronic and Information Engineering, B.Eng.
Employment
2026.11 – PresentSouthern University of Science and Technology, Department of Electronic and Electrical Engineering, Tenured Associate Professor
2022.11 – 2026.11Southern University of Science and Technology, Department of Electronic and Electrical Engineering, Tenure-Track Associate Professor
2021.03 – 2022.11Southern University of Science and Technology, Department of Electronic and Electrical Engineering, Assistant Professor
2018.01 – 2021.02Texas Instruments, Kilby Labs Silicon Valley, Analog Design Engineer
2017.09 – 2017.12The Hong Kong University of Science and Technology (HKUST), Postdoctoral Fellow
Research Areas
Research Fields: Analog and Power Integrated Circuits Design, Power Management ICs, Integrated Power Electronics, AI-Assisted EDA Design
1.
Ultra-High Current Density Power ICs for AI Computing and Processors (Power IC for AI)
Focusing on ultra-high conversion ratios, extreme power density, and microsecond-level fast transient response; researching Vertical Power Delivery (VPD) architectures and key ICs for AI accelerators and high-performance processors; developing intermediate bus converters (IBC), integrated power stages (DrMOS), integrated voltage regulators (IVR), and Sigma/hybrid converter chips to conquer power delivery bottlenecks in next-generation computing systems.
2.
AI-Driven Automated Analog and Power IC Design (AI for Power IC / EDA)
Integrating multi-agent reinforcement learning (MARL) and automated layout generation algorithms to address engineering bottlenecks in analog circuit sizing and physical layout generation, advancing analog circuit design from human-experience-driven to AI-automated workflows.
3.
Special High-Voltage and Advanced Display Driver Power Management Systems (Power IC for Specific Applications)
Targeting emerging frontiers such as Micro-LED displays, automotive LiDAR, and surface acoustic wave devices; developing specialized high-performance driver and power management ICs featuring wide voltage ranges, high energy conversion efficiency, and ultra-high integration.
Honors and Awards
1.
2026, IEEE Custom Integrated Circuits Conference (CICC) Best Paper Award
2.
2026, IEEE/ACM ASP-DAC Best Design Contest Award
3.
2026, IEEE ICSICT IC Design Competition 1st Award
4.
2026, Top 10 Semiconductor Research Advances in China (Nomination Award)
5.
2025, Outstanding Residential College Mentor Award, SUSTech
6.
2025, IEEE ISSCC Silkroad Award (Co-recipient)
7.
2024, Outstanding Teaching Award, SUSTech
8.
2023, Shenzhen Industrial Development and Innovation Talent Award
9.
2022, National-Level Overseas High-Level Young Talent
10.
2021, Shenzhen Overseas High-Level Talent (Peacock Plan, Class C)
11.
2018, ASP-DAC University LSI Design Contest Special Feature Award
12.
2017, IEEE Solid-State Circuits Society (SSCS) Pre-Doctoral Achievement Award
13.
2015, Analog Devices Inc. (ADI) Outstanding Student Designer Award
Representative Publications(Underlined: supervised students, *: corresponding author)
1.
G. Liu, J. Jiang*, S. Du, X. Liu* ·IEEE International Solid-State Circuits Conference (ISSCC), vol. 69, pp. 336-338, 2026
2.
ISSCC 2025A 93%-Peak-Efficiency Battery-Input 12-to-36V-Output Inductor-in-the-Middle Hybrid Boost Converter with Continuous Input and Output Currents and Fast Transient with No RHP Zero Top 10 Semiconductor Research Advances in China (Nomination Award)
Y. Jiang, Y. Lu*, T. Tang, J. Jiang* ·IEEE International Solid-State Circuits Conference (ISSCC), vol. 68, pp. 196-198, 2025
3.
G. Liu, H. Wu, C. Hu, C. Huang, X. Liu, J. Jiang* ·IEEE International Solid-State Circuits Conference (ISSCC), vol. 67, pp. 512-513, 2024
4.
C. Hu, X. Huang, X. Liu, S. Du, X. Liu, J. Jiang* ·IEEE International Solid-State Circuits Conference (ISSCC), vol. 67, pp. 508-509, 2024
5.
C. Hu, X. Huang, X. Liu, S. Du, X. Liu, J. Jiang* ·IEEE Journal of Solid-State Circuits (JSSC), vol. 61, no. 7, pp. 3577-3588, 2026
6.
G. Liu, H. Wu, C. Hu, Y. Zhong, C. Huang, X. Liu, J. Jiang* ·IEEE Journal of Solid-State Circuits (JSSC), vol. 61, no. 6, pp. 2775-2786, 2026
7.
Y. Li, J. Jin, Y. Guo, J. Zhou, J. Jiang* ·IEEE Journal of Solid-State Circuits (JSSC), vol. 61, no. 2, pp. 641-650, 2026
8.
Y. Jiang, Y. Lu, C. Hu, J. Jiang* ·IEEE Journal of Solid-State Circuits (JSSC), vol. 60, no. 9, pp. 3305-3316, 2025
9.
X. Yan, G. Liu, C. Hu, K. Zhu, Z. Liu, X. Liu, J. Jiang* ·IEEE Transactions on Power Electronics (TPEL), vol. 40, no. 10, pp. 14388-14400, 2025
10.
Y. Jiang, Y. Lu, J. Jiang* ·IEEE Transactions on Power Electronics (TPEL), vol. 38, no. 11, pp. 13886-13898, 2023
11.
C. Hu, W. Song, S. Du, X. Liu, J. Jiang* ·IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 72, no. 11, pp. 6458-6468, 2025
12.
Y. Shi, X. Liu, C. Hu, X. Tang, J. Jiang* ·IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 72, no. 6, pp. 2520-2528, 2025
13.
Y. Jiang, Y. Lu, J. Jiang* ·IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 71, no. 12, pp. 5683-5693, 2024
For full publications, please visit: Google Scholar Profile | Group Homepage (PICL)
Academic Services & Community
1.
Chair, IEEE Circuits and Systems Society (CASS) Shenzhen Chapter
2.
Associate Editor, IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)
3.
Guest Editor, IEEE ISCAS 2022, ISICAS 2022 Special Issues
4.
Technical Program Committee (TPC) Member, IEEE CICC, IEEE ISCAS, IEEE ICTA, IEEE ICSICT
Openings & Opportunities
Power Integrated Circuits Laboratory (PICL) is dedicated to cutting-edge research on analog/mixed-signal ICs, power management, and integrated power electronics. Our lab provides advanced technology tape-outs and comprehensive experimental platforms, maintaining close collaboration with leading industry companies (Texas Instruments, Qualcomm, ADI, etc.) and prestigious international universities.
1.
Graduate & Undergraduate Student Admissions
We are actively recruiting Ph.D. students (including Fast-Track Ph.D. programs) and Master's students for Fall 2027. Motivated undergraduate students are always welcome to join us for research training, Capstone projects, and internships. Prospective students with strong academic backgrounds and passion for IC design are encouraged to contact Dr. Jiang.
2.
Research Faculty & Postdoctoral Positions
Openings are available year-round for Research Assistant Professors, Postdoctoral Fellows (with internationally competitive salary and substantial government subsidies), and Research Assistants. Researchers with expertise in analog ICs, power electronics, and EDA are warmly invited to apply.
Contact Email: jiangjm@sustech.edu.cn
Office: Room 427, South Tower, College of Engineering, SUSTech
Office: Room 427, South Tower, College of Engineering, SUSTech