Faculty

YU Hongyu
Professor
The Institute of Engineering and Technology Fellow
Dean of School of Microelectronics
yuhy@sustech.edu.cn

Hongyu Yu, currently serves as Professor and Dean of School Of Microelectronics and Deputy Director of Shenzhen Institute Of Wide Gap Semiconductors. He has set up for SUSTech-HKUST Joint School of Microelectronics and the third of generation semiconductor research institute in Shenzhen. On behalf of Southern University of Science and Technology, he set up the 5G Innovation Center of Medium and High Frequency Device Manufacturing Industry with Tsinghua University. In collaboration with University of Hong Kong, University of Macau and Hong Kong University of Science and Technology, he enrolled the first experimental class. Established shenzhen third-generation semiconductor key laboratory, Guangdong province GaN device engineering technology center, and served as director. He has been awarded with the "1000 Talents Program for Young Scholars", Peacock project Shenzhen, Pengcheng scholar, Fellow of IET, special government allowance, deputy editor of Science Bulletin(China's top comprehensive academic journal) and editor of Journal of Semicondictor.
He received his BSc, MSc, and PhD from Tsinghua University, University of Toronto, and National University of Singapore, respectively. He is a senior researcher in IMEC Belgium 2004 to 2008. From 2008 to 2011, he served as a assistant professor in the department of Electrical and Electronics Engineering, NanYang Technological University, Singapore.
Professor Yu Hongyu has achieved a series of innovative work in integrated circuit technology and devices, including CMOS, new ultra-high density memory, GaN device and system integration (GaN HEMT). He published more than 370 papers (>160 journal papers + >170 conference papers) with a SCI H-index of 38;Written 4 book chapters, edited 2 books: “Hafnium: Chemical Characteristics, Production and Application” and “Gallium Nitride Power Devices”. Applied/authorized 20 US/European patents and more than 10 Chinese patents. As a PI, he has undertaken ~20 research/talent projects, with a total funding ~ 70 million RMB. He has built a 1,200-square-metre clean room in Southern University of Science and Technology, forming a full 6-inch CMOS lab which hardware will reach the top level in southern China.

 

Education
2004 Ph.D. Department of Electrical and Computer Engineering, National University of Singapore
2001 M.S. Department of Materials Science and Engineering, University of Toronto
1999 B.A. Department of Materials Science and Engineering, Tsinghua University

 

Working Experiences
2011-Present, Professor, Southern University of Science and Technology

2018-Present,  Director of School of  Microelectronics, and Vice President of the Shenzhen Wide  Semiconductor Research Institute.

2008-2011, Assistant Professor & Nano Devices Laboratory Deputy Director, Microelectronic Department, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore

2004-2008, Senior Researcher & PI IMEC (World-renowned micro-Nano electronic research and development center), Leuven, Belgium

2003-2004, Research & Development Engineer Department of Electrical Engineering, National University of Singapore

 

Research Introduction
GaN power device and system integration
Multi-layer Ceramic Capacitor
Advanced CMOS process
New Ultra-high Density Memory

 

Awards & Honors
Outstanding Scientific Research Award in South University of Science and Technology (2016)
B Leading Talent of Nanshan District, Shenzhen (2016)
Pengcheng scholar (2014)
Peacock Project ,Shenzhen (2013)
Shenzhen government special allowance (2012)
Fellow of IET (2012)
Senior Member of IEEE (2012)
State Specially Recruited Expert( Youth Talent Plan)(2011)
MRS-ICMAT Best Poster Award: Solar Cell (2011)
The Recruitment Program of Global Experts (Young Scholar Program), Organization Department of the CCCPC (2011)
Chen Zhenchuan Academic Exchange Award (2009)
Nanyang Assistant Professorship, NTU (2008)
Highlight paper in Symposium on VLSI Technology, (2007, Kyoto, Japan)
IEEE Electron Device Society (EDS) Graduate Fellowship (2004, USA)
President of NUS Scholarship(2002)

 

Papers
1.H.Y. Yu*, X.D. Feng, D. Grozea, Z.H. Lu, R. Sodhi, A.M. Hor, H. Aziz. Surface electronic structure of plasma-treated indium tin oxides. Applied Physics Letters, 2001, 78(17): 2595-2597
2.H.Y. Yu*, M.F. Li, B.J. Cho, C.C. Yeo, M.S. Joo, D.L. Kwong, J.S. Pan, C.H. Ang, J.Z. Zheng, S. Ramanathan. Energy gap and band alignment for (HfO2)x(Al2O3)1-x on (100) Si. Applied Physics Letters, 2001, 81(2): 376-378
3.H.Y. Yu*, N. Wu, M.F. Li, C.X. Zhu, B.J. Cho, D.L. Kwong, C.H. Tung, J.S. Pan, J.W. Chai, W.D. Wang, D.Z. Chi, S. Ramanathan. Thermal stability of (HfO2)x(Al2O3)1-x on Si. Applied Physics Letters, 2002, 81(19): 3618-3620
4.H.Y. Yu*, Y.T. Hou, M.F. Li, D.L. Kwong. Hole tunneling current through oxynitride/oxide stack and the stack optimization for p-MOSFETs. IEEE Electron Device Letters, 2002, 23(5):285-287
5.Y.T. Hou*, M.F. Li, H.Y. Yu, D.L. Kwong. Modeling of tunneling currents through HfO2 and (HfO2)x(Al2O3)1-x gate stacks. IEEE Electron Device Letters, 2003, 24(2): 96-98
6.H.Y. Yu*, H.F. Lim, J.H. Chen, M.F. Li, C.X. Zhu, C.H. Tung, A. Du, W. Wang, D. Chi, D.L. Kwong. Physical and electrical characteristic of HfN gate electrode for advanced MOS devices. IEEE Electron Device Letters, 2003, 24(4): 230-232
7.M.S. Joo, B.J. Cho*, C.C. Yeo, N. Wu, H.Y. Yu, C.X. Zhu, M.F. Li, D.L. Kwong, N. Balasubramanian. Dependence of chemical composition ratio on electrical properties of HfO2-A2O3 gate dielectric. Japanese Journal of Applied Physics Part 2-Letters & Express Letters, 2003, 42(3A):220-222
8.H.Y. Yu*, J.F. Kang, C. Ren, J.D. Chen, Y.T. Hou, C. Shen, M.F. Li, D.S.H. Chan, K.L. Bera, C.H. Tung, D.L. Kwong. Robust high-quality HfN-HfO2 gate stack for advanced MOS device applications. IEEE Electron Device Letters, 2004, 25(2): 70-72
9.J.F. Kang*, H.Y. Yu, C. Ren, M.F. Li, DSH. Chan, H. Hu, H.F. Lim, W.D. Wang, D. Gui, D.L. Kwong. Thermal Stability of nitrogen incorporated in HfNxOy gate dielectrics by reactive sputtering. Applied Physics Letters, 2004, 84(9): 1588-1590
10.C. Ren, H.Y. Yu, J.F. Kang, Y.T. Hou, D.S.H. Chan*, M.F. Li, W.D. Wang, D.L. Kwong. Fermi-level pinning induced thermal instability in the effective work function of TaN in TaN/SiO2 gate stack. IEEE Electron Device Letters, 2004, 25(3): 123-125
11.H.Y. Yu, C. Ren, Y.C. Yeo, J.F. Kang, X.P. Wang, H.H.H. Ma, M.F. Li*, D.S.H. Chan, D.L. Kwong. Fermi level-pinning induced thermal instability of metal gate work functions. IEEE Electron Device Letters, 2004, 25(5): 337-339
12.S.Y. Zhu*, H.Y. Yu, S.J. Whang, J.H. Chen, C. Shen, C.X. Zhu, S.J. Lee, M.F. Li, D.S.H. Chan, W.J. Yoo. A. Du, C.H. Tung, J. Singh, A. Chin, D.L. Kwong, Schottky-barrier S/D MOSFETs with high-K gate dielectrics and metal gate electrode. IEEE Electron Device Letters, 2004, 25(5): 268-270
13.C. Ren*, H.Y. Yu, J.F. Kang, X.P. Wang, H.H.H. Ma, Y.C. Yeo, M.F. Li, D.S.H. Chan, D.L. Kwong. A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO2 by using HfN replacement gate. IEEE Electron Device Letters, 2004, 25(8): 580-582
14.C. Ren*, H.Y. Yu, X.P. Wang, H.H. Ma, D.S.H. Chan, M.F. Li, Y.C. Yeo, C.H. Tung, N. Balasubramanian, A.C.H. Huan, J.S. Pan, D.L. Kwong. Thermally robust TaTbxN metal gate electrode for n-MOSFETs applications. IEEE Electron Device Letters, 2005, 26(2): 75-77
15.C. Shen, M.F. Li*, H.Y. Yu, X.P. Wang, Y.C. Yeo, D.S.H. Chan, D.L. Kwong. Physical model for frequency-dependent dynamic charge trapping in metaloxide-semiconductor field effect transistors with HfO2 gate dielectric.
Applied Physics Letters, 2005, 86(9), 093510
16.J.F. Kang*, H.Y. Yu, C. Ren, X.P. Wang, M.F. Li, D.S.H. Chan, Y.C. Yeo, N. Sa, H. Yang, X.Y. Liu, R.Q. Han, D.L. Kwong. Improved electrical and reliability characteristics of HfN-HfO2-gated nMOSFET with 0.95-nm EOT fabricated using a gate-first process. IEEE Electron Device Letters, 2005, 26(4): 237-239
17.N. Sa*, J.F. Kang, H. Yang, X.Y. Liu, Y.D. He, R.Q. Han, C. Ren, H.Y. Yu, D.S.H. Chan, D.L. Kwong. Mechanism of positive-bias temperature instability in sub-1-nm TaN/HfN/HfO2 gate stack with low preexisting traps. IEEE Electron Device Letters, 2005, 26(9): 610-612
18.J.F. Kang*, H.Y. Yu, C. Ren, M.F. Li, D.S.H. Chan, X.Y. Liu, D.L. Kwong. Ultrathin HfO2(EOT <0.75nm) gate stack with TaN/HfN electrodes fabricated using a high-temperature process. Electrochemical and Solid-State Letters, 2005, 8(11): G311-313.
19.J.F. Kang*, H.Y. Yu, C. Ren, X.Y. Liu, R.Q. Han, B. Yu, D.L. Kwong. An improved pregate cleaning process for high-k gate dielectric fabrication. Electrochemical and Solid-State Letters, 2005, 8(11): G314-316
20.J.D. Chen, H.Y. Yu*, M.F. Li, D.L. Kwong, M. van Dal, J.A. Kittl, A. Lauwers, P. Absil, M. Jurczak, S. Biesemans. Yb-doped NiFUSI for the n-MOSFETs gate electrode application. IEEE Electron Device Letters, 2006, 27(3): 160-162